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CMOS Static RAM 256K (64K x 4-Bit)
IDT61298SA
x x
Features
64K x 4 high-speed static RAM Fast Output Enable (OE) pin available for added system flexibility High speed (equal access and cycle times) - Commercial: 12/15 ns (max.) JEDEC standard pinout 300 mil 28-pin SOJ Produced with advanced CMOS technology Bidirectional data inputs and outputs Inputs/Outputs TTL-compatible Three-state outputs Military product compliant to MIL-STD-883, Class B CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective approach for memory intensive applications. The IDT61298SA features two memory control functions: Chip Select (CS) and Output Enable (OE). These two functions greatly enhance the IDT61298SA's overall flexibility in high-speed memory applications. Access times as fast as 12ns are available. The IDT61298SA offers a reduced power standby mode, ISB1, which enables the designer to considerably reduce device power requirements. This capability significantly decreases system power and cooling levels, while greatly enhancing system reliability. All inputs and outputs are TTL-compatible and the device operates from a single 5V supply. Fully static asynchronous circuitry, along with matching access and cycle times, favor the simplified system design approach. The IDT61298SA is packaged in a 300 mil, 28-pin SOJ, providing improved board-level packing densities.
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Description
The lDT61298SA is a 262,144-bit high-speed static RAM organized as 64K x 4. It is fabricated using IDT's high-performance, high-reliability
Functional Block Diagram
A0 VCC D E C O D E R A15 GND 262,144-BIT MEMORY ARRAY
I/O0 I/O1 I/O2 I/O3
I/O CONTROL INPUT DATA CONTROL
,
CS WE OE
2971 drw 01
FEBRUARY 2001
1
(c)2000 Integrated Device Technology, Inc. DSC-2971/08
IDT61298SA CMOS Static RAM 256K (64K x 4-Bit)
Commercial Temperature Range
Pin Configuration
NC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 CS OE GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22
Truth Table
CS OE L X H X
(3)
(1,2)
WE H L H X X
I/O DATAOUT DATAIN High-Z High-Z High-Z
Function Read Data Write Data Outputs Disabled Deselected - Standby (ISB) Deselecte d - Standby (ISB1)
2971 tbl 02
SO28-5
21 20 19 18 17 16 15
VCC A15 A14 A13 A12 A11 A10 NC NC I/O3 I/O2 I/O1 I/O0 WE
2971 drw 02
L L L H VHC
X
NOTES: 1. H = VIH, L = VIL, x = Don't care. 2. VLC = 0.2V, VHC = VCC -0.2V. 3. Other inputs VHC or VLC.
,
Absolute Maximum Ratings(1)
Symbol VTERM TA TBIAS TSTG PT
(2)
Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
Com'l. -0.5 to +7.0 0 to +70 -55 to +125 -55 to +125 1.0 50
Unit V
o o
SOJ Top View
C C C
o
W mA
2971 tbl 03
Pin Descriptions
Name A0 - A14 I/O0 - I/O7 CS WE OE GND VCC Description Addresses Data Input/Output Chip Select Write Enable Output Enable Ground Power
2971 tbl 01
IOUT
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 0.5V.
(TA = +25C, f = 1.0MHz, SOJ Package)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 5 7 Unit pF pF
2971 tbl 04
Capacitance
NOTE: 1. This parameter is determined by device characterization, but is not production tested.
2
IDT61298SA CMOS Static RAM 256K (64K x 4-Bit)
Commercial Temperature Range
Recommended Operating Temperature and Supply Voltage
Grade Commercial Temperature 0OC to +70OC GND 0V Vcc 5V 10%
2971 tbl 05
Recommended DC Operating Conditions
Symbol VCC GND VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5(1) Typ. 5.0 0
____
Max. 5.5 0 VCC + 0.5V 0.8
Unit V V V V
2971 tbl 06
____
NOTE: 1. VIL (min.) = -1.5V for pulse width less than 10ns, once per cycle.
DC Electrical Characteristics(1)
(VCC = 5V 10%, VLC = 0.2V, VHC = VCC - 0.2V)
61298SA12 Symbol ICC ISB ISB1 Parameter Dynamic Operating Current CS < VIL, Outputs Open, VCC = Max., f = fMAX(2) Standby Power Supply Current (TTL Level) CS > VIH, VCC = Max., Outputs Open, f = fMAX(2) Full Standby Power Supply Current (CMOS Level) CS > VHC, VCC = Max., f = 0(2), VIN < VLC or VIN > VHC Com'l. 160 50 20 61298SA15 Com'l. 140 45 20 Unit mA mA mA
2971 tbl 07
NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2
2971 tbl 08
5V 480 DATA OUT 255 30pF* DATA OUT 255
5V 480
5pF*
2971 drw 03
,
*Includes scope and jig capacitances
,
2971 drw 04
Figure 1. AC Test Load
Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, tWHZ)
6.42 3
IDT61298SA CMOS Static RAM 256K (64K x 4-Bit)
Commercial Temperature Range
DC Electrical Characteristics
(VCC = 5.0V 10%)
Symbol |ILI| |ILO| VOL VOH IDT61298SA Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Conditions VCC = Max., VIN = GND to VCC VCC = Max., CS = VIH, VOUT = GND to VCC IOL = 8mA, VCC = Min. IOL = 10mA, VCC = Min. IOH = -4mA, VCC = Min. Min.
____
Typ.
____
Max. 5 5 0.4 0.5
___
Unit A A V V
2971 tbl 09
____
____
____ ____
____ ____
2.4
___
AC Electrical Characteristics
Symbol
(VCC = 5.0V 10%)
61298SA12 61298SA15 Min. Max. Unit
Parameter
Min.
Max.
Read Cycle
tRC tAA tACS tCLZ(1) tCHZ(1) tOE tOLZ(1) tOHZ(1) tOH tPU(1) tPD(1) Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low-Z Chip Desele ct to Output in High-Z Output Enable to Output Valid Output Enab le to Output in Low-Z Output Disab le to Output in High-Z Output Hold from Address Change Chip Select to Power-Up Time Chip Deselect to Power-Down Time 12
____ ____
15
____
____
ns ns ns ns ns ns ns ns ns ns ns
12 12
____
15 15
____
____
____
4
____
4
____
6 6
____
7 7
____
____
____
0
____
0
____
6
____
6
____
3 0
____
3 0
____
____
____
12
15
Write Cycle
tWC tCW tAW tAS tWP tWR tDW tDH tWHZ(1) tOW(1) Write Cycle Time Chip Select to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Data Hold Time Write Enab le to Output in High-Z Output Active from End-of-Write 12 9 9 0 9 0 6 0
____ ____
15 10 10 0 10 0 7 0
____
____
ns ns ns ns ns ns ns ns ns ns
2971 tbl 10
____
____
____ ____
____ ____
____
____
____ ____
____ ____
____
____
6
____
6
____
4
4
NOTE: 1. This parameter is guaranteed with AC test load (Figure 2) by device characterization, but is not production tested.
4
IDT61298SA CMOS Static RAM 256K (64K x 4-Bit)
Commercial Temperature Range
Timing Waveform of Read Cycle No. 1(1)
t RC ADDRESS tAA OE t OLZ CS t ACS t CLZ DATA OUT
(5)
t OH
t OE (5)
t OHZ
(5)
t CHZ DATA VALID
(5)
2971 drw 05
,
Timing Waveform of Read Cycle No. 2(1,2,4)
tRC ADDRESS tAA tOH DATAOUT DATA VALID
2971 drw 06
tOH
,
Timing Waveform of Read Cycle No. 3(1,3,4)
CS t ACS t CLZ (5) DATAOUT t PU VCC ICC SUPPLY CURRENT ISB
2971 drw 07
t CHZ DATA VALID t PD
(5)
,
NOTES: 1. WE is HIGH for Read cycle. 2. Device is continuously selected, CS is LOW. 3. Address valid prior to or coincident with CS transition LOW. 4. OE is LOW. 5. Transition is measured 200mV from steady state.
6.42 5
IDT61298SA CMOS Static RAM 256K (64K x 4-Bit)
Commercial Temperature Range
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
tWC ADDRESS tAW CS tAS WE tWHZ DATAOUT
(3) (5)
tWP
(2)
tWR
tOW
(5) (3)
tDW DATAIN
tDH
DATA VALID
2971 drw 08
,
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4)
tWC ADDRESS tAW CS tAS WE tDW DATAIN DATA VALID
2971 drw 09
tCW
tWR
tDH
,
NOTES: 1. A write occurs during the overlap of a LOW CS and a LOW WE. 2. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the spectified tWP. 3. During this period, I/O pins are in the output state so that the input signals must not be applied. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured 200mV from steady state.
6
IDT61298SA CMOS Static RAM 256K (64K x 4-Bit)
Commercial Temperature Range
Ordering Information
IDT 61298 Device Type SA Power XX Speed XX Package X Process/ Temperature Range Blank Commercial (0C to +70C)
Y
300-mil SOJ (SO28-5)
12 15
Speed in nanoseconds
2971 drw 10
,
6.42 7
IDT61298SA CMOS Static RAM 256K (64K x 4-Bit)
Commercial Temperature Range
Datasheet Document History
11/22/99: Pg. 6 Pg. 7 08/09/00 02/01/01 Updated to new format Removed Note No. 1 Write Cycle No. 1 diagram, renumbered notes and footnotes Added Datasheet Document History Not recommended for new designs Removed "Not recommended for new designs"
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